1. Field of the Invention
The present invention relates generally to electrically conductive feed-throughs in a body of semiconductor material, and more particularly, to a method and structure of forming electrically conductive interconnections through a body of semiconductor material which provide means of electrically connecting coplanar surfaces of a body of semiconductor material while concurrently providing means of making mechanical, electrical, and thermal external connections to a body of semiconductor material.
2. Description of the Related Art
Packaging and interconnecting of electronic systems and sub-systems greatly influence their performance, reliability, and cost.
Performance of electronic systems and sub-systems are measured by their speed and capacity of data processing. Such systems generally comprise electronic devices such as transistors which have an inherent response time to the electrical signals. However, the time it takes for an electrical signal to travel from one electronic device to another significantly plays a role in the system performance. Long electrical signal interconnection paths not only prolong propagational delays and increase susceptibility to noise, it also requires more power dissipation and degrades the entire system performance in general. For these reasons, more integrated circuits are fabricated on a large integrated scale. As a consequence, performance is upgraded as the aforementioned drawbacks are minimized. Reliability is also improved as a result since the number of off-chip interconnections are decreased. These off-chip interconnections are major source of mechanical and electrical failures. Above all, cost is substantially curtailed as the required wiring schemes are simplified. An electronic system or sub-system may comprise a variety of electronic components. These components may be fabricated on various materials such as silicon, germanium, or gallium arsenide. Very often, it is impossible for these various components to be integrated on a single substrate due to performance consideration or cost concern. Consequently, these electronic components are packaged and electrically interconnected together externally to function as a unity.
There are inventions in the past with electronic components stacked together and electrical communication between components are made possible via the feed-throughs in the semiconductor bodies. The assembled stacks are then attached onto a printed circuit board which has long routing traces and with all the associated shortfalls as mentioned. Moreover, the thermal coefficients of the assembled stacks and the printed circuit board are not always compatible, resulting in subsequent thermal mismatches and consequently reliability problems.
In general, the feed-throughs of most prior art structures are formed by first drilling holes into the semiconductor substrate. The side-walls of the holes are then insulated. Finally, conductive materials are deposited into the holes to transform the feed-through into electrically conductive paths. The holes can be drilled by a variety of methods. Examples include laser drilling, abrasive jet blasting, or chemical etching. The insulation on the sidewalls of the holes are commonly formed from the processes of oxidation or coating. The conductive filling inside the holes can be metal deposition by the processes of Chemical Vapor Deposition (CVD), or sputtering. Alternatively, the conductive filling can be also be an alloy such as lead-tin solder formed by submerging the holes in a molten solder path.
Examples of the aforementioned structure with feed-throughs are taught in U.S. Pat. No. 4,074,342, entitled "Electrical Package for LSI Devices and Assembly Process Thereof" to Honn et al, Feb. 14, 1978; and U.S. Pat. No. 4,535,424, entitled "Solid State Three Dimensional Semiconductor Memory Array" to Reid, Aug. 13, 1985.
Other information of electrically conductive interconnections through a body of semiconductor material includes a publication by Anthony et al., in the Journal of Applied Physics, Vol. 52 No. 8 pages 5340-5349, August 1981, entitled "Forming Electrical Interconnections Through Semiconductor Wafers".
Alternatively, the feed-through can be formed by the process of thermomigration. Essentially, it is a process in which a thermal gradient is applied across the two opposite planer surfaces of a semiconductor substrate, and in which the conductive material, migrates from one surface to the other along the direction of the thermal gradient. Examples of the thermomigration process can be found in U.S. Pat. No. 4,239,312, entitled "Parallel interconnection for Planar Arrays" to Myer et al., Dec. 16, 1980; U.S. Pat. No. 4,275,410, entitled "Three-Dimensional Structured Microelectronic Device" to Grinberg et al., Jun. 23, 1981; U.S. Pat. No. 2,770,761, entitled "Semiconductor Translators Containing Enclosed Active Junctions" to Pfann, Nov. 13, 1956; U.S. Pat. No. 3,895,967, entitled "Semiconductor Device Production" to Anthony et al., Jul. 22, 1975; U.S. Pat. No. 3,899,361, entitled "Stabilized Droplet Method of Making Deep Diodes Having Uniform Electrical Properties" to Cline et al., Aug. 12, 1975; and U.S. Pat. No. 3,904,442, entitled "Method of Making Isolated Grids in Bodies of Semiconductor Material" to Anthony et al., Sep. 9, 1975. Further teachings on the thermomigration process can be found in technical papers such as in the Journal of Applied Physics: Vol. 47, No. 6, pages 2316-2324, February 1976, entitled "Random Walk of Liquid Droplets Migrating in Silicon"; Vol. 47, No. 6, pages 2325-2331, February 1976, entitled "High-Speed Droplet Migrating in Silicon"; Vol. 47, No. 6, pages 2332-2336, February 1976, entitled "Thermomigration of Aluminum-Rich Liquid Wires Through Silicon"; Vol. 48, No. 9, pages 3943-3949, April 1977, entitled "Laminar Devices Processed by Thermomigration"; Vol. 49, No. 4, pages 2412-2419, November 1976, entitled "Migration on Fine Molten Wires in Thin Silicon Wafers"; Vol. 49, No. 5, pages 2777-2786, May 1978, entitled "On The Thermomigration of Liquid Wires"; and Vol. 49, No. 12, pages 5774-5782, December 1978, entitled "Stresses Generated by Thermomigration of Liquid Inclusions in Silicon". The aforementioned documents primarily focus on thermomigration as a means of fabrication P-N junctions and the electronic devices which might result.
In the aforementioned U.S. Pat. Nos. 4,239,312 and 4,275,410, computer architecture of electrically interconnecting a plurality of stacked integrated circuit wafers by means of spring contacts are disclosed. These spring contacts are attached on both sides of a wafer after first thermomigrating electrical feed-through from one side of the wafer to the other side of the wafer. External electrical interconnections are made possible by pressing the springs of one circuit wafer to the bonding pads of an adjacent wafer.
It is an objective of the present invention to reduce the length of electrical interconnections between bodies of semiconductor material and thereby improving the performance of signal communication. Another objective of the present invention is to upgrade the reliability of electrical interconnections by reducing discontinuities in electronic signal paths between the bodies of semiconductor material. A further objective of the present invention is to provide an improved thermal management between the bodies of semiconductor material. A still further objective of the present invention is to facilitate the dense use of electrical signal routing paths by means of existent semiconductor processing technology. A still further objective of the present invention is to reduced number of fabrication steps and thereby curtails production cost.